1. Field of the Invention
The present invention relates to a computer program product, system, and method for determining processor offsets to synchronize processor time values.
2. Description of the Related Art
In a multi-core processor, multiple processors or cores are implemented on a single integrated circuit substrate, i.e., chip, and each processor core has registers, an L1 cache, and memory interface with a shared memory, such as an L2 cache. A common clock may provide clock signals to all the cores. The processor cores maintain time values in local registers that are incremented in response to the clock signal. However, the cores may not start at the same time and the time value at each processor core may differ. Certain applications may want the processor cores to have a synchronized time value.
Various prior art synchronization techniques pose problems in a multi-core environment. For instance, freezing the processor registers having the time values is problematic because there is the risk of an interrupt being generated while the time value registers are frozen. If an interrupt occurs, then all time related entries resulting from the interrupt operation will have the same time values even if the operations occur at different times. Further, while the time registers of the processors are frozen, a host adapter's time values will appear to move backwards in relation to externally connected agents, since the connected agents time values will still be advancing forward. Yet further, a master processor core registers cannot be rewound because the timeline of the master processor would appear to move backwards, including in relation to externally connected agents.
There is a need in the art for improved techniques to synchronize the time values maintained for the processor cores.